Hi, I'm new here.
I want to know how I can stream video from a camera (installed on Zedboard) to the USB UART, it's the first time with this kind of work so I hope someone can help me.
I just know that is possible using uvc protocol like the image Sensor Interface Using EZ-USB FX3, but I don't now how I can implement it on CY7C64225.
Thanks.
I recently purchased EZ-USB FX3 CYUSB3KIT-001 development kit. I use Microsoft's routine USBSamp as a USB driver, and i have written an applications. Now i use Cypress's firmware USBBulkSourceSink to test the application and driver, but communication rates up to only 4M/s or so .This rate is far from the high-speed（60M/s）.Then I noticed some tips of firmware：
"The default example is not optimized for performance in USB 3.0, in order to get better performance the following changes has to be done.
1. Have only 1 endpoint (IN or OUT) .This avoids any USB host bandwidth issues.
2. Update the "Max. no. of packets in a Burst" field (1 to 15) in the "Super Speed Endpoint Companion Descriptor" in cyfxbulkdscr.c.
3. In cyfxbulksrcsink.c change the dmaCfg.size by factor of ("Max. no. of packets in a Burst" field in the "Super Speed Endpoint Companion Descriptor" + 1) for USB 3.0. The performance will be better if this is twice the size of the burst ie. (2 * ("Max. no. of packets in a Burst" field in the "Super Speed Endpoint Companion Descriptor" + 1)). When making these changes, make sure that there is enough memory available for buffering.
4. In cyfxbulksrcsink.c change epCfg.burstLen to "Max. no. of packets in a Burst" field in the "Super Speed Endpoint Companion Descriptor" + 1, before calling CyU3PSetEpConfig."
So I try this method，but i am failed! Downloading the program is unsuccessful！ I do not know why!
For my example : Max. No. Of packets in a Burst value is set to 15,
dmaCfg.size value is set to 32,
epCfg.burstLen value is set to 16.
Where is wrong in this example ? How should i set up the firmware to improve communication rate? Thank you !
Apologies if this has been answered elsewhere but I have been unable to find anything. I am new to the CyAPI and am trying to write a C++ application to communicate with a CY7C68013A. However, whenever I attempt a read/write to the control endpoint, I see an error 997. The functional part of my code is here:
CCyControlEndPoint *ept = USBDevice->ControlEndPt;
ept->Target = TGT_DEVICE;
ept->ReqType = REQ_VENDOR;
ept->Direction = DIR_TO_DEVICE;
ept->ReqCode = 0xA0;
ept->Index = 0x0000;
unsigned char buf[64];
ZeroMemory(buf, 64);
ept->Value = 0xE600;
LONG buflen = 1;
buf[0] = 1;
ept->XferData(buf, buflen);ept->Direction = DIR_FROM_DEVICE;
ept->Value = 0xE60A;
buflen = 1;ept->XferData(buf, buflen);
cout << "Data: "<< hex << (int)buf[0] << dec << "\nError code: "<< ept->LastError << '\n';
According to the documentation I've seen, this register should output a value of "1"; however, I get "5e". In fact, for any register I try to access, I get "5e 6f" repeating. Is there something I am missing about setting up the control endpoint or how I'm using it?
Thanks,
Scott
Is there is any utlity which converts eeprom iic file to intel hex
Hello,
I have a camera mainly composed of a CMOS connected to my FX2LP.
The CMOS' output is connected to FD through PORTB.
I use the FX2 as master for the camera grab:
1 - Insert frame header in EP2 FIFO
2 - Trigger CMOS
3 - Wait frame readout done
4 - Go to step 1
It works, but after header insertion a 6 bytes (header size) packet is immediately sent. Bulk transfer ends when transfer size is reached or an incomplete/zero-length is sent. So, the host interprets it as the end of the communication.
Header insertion code snippet:
EP2FIFOBUF[0] = 255;
EP2FIFOBUF[1] = 0;
EP2FIFOBUF[2] = 0;
EP2FIFOBUF[3] = 255;
EP2FIFOBUF[4] = frame_id >> 8;
EP2FIFOBUF[5] = frame_id & 0xFF;
SYNCDELAY;
EP2BCH = 0x00;
SYNCDELAY;
EP2BCL = 0x06;
SYNCDELAY;
I tried to disable AUTOIN, write the header and wait until FIFO reach at least 512B (packet size) before re-enabling AUTOIN. Unfortunately, I miss all headers. It looks like that when I commit data to the FIFO from the CPU, it doesn't increment FIFO pointer from a slave interface point of view. So, the header is orverride when the CMOS outputs the frame content.
Is there any way to insert data from the CPU and wait slave interface complete the packet before sending it?
If there is still data pending in the FIFO when I write my header (see snippet), will I override it?
I still have a way to deal with it from a host point of view. But since it brakes end of bulk transfer condition, I prefer to fix it in the frimware.
Thanks for taking time on my problem.
Hello all,
is it possible to force a reboot from I2C without powering down the device or toggling the hardware reset pin ?
During production of our boards the FX2LP boots with an empty I2C eeprom. With the USB Control Center application (or our own software using the cypress library functions) the firmware is written into the eeprom. But this is not yet actually running this new firmware (which is needed for the next steps of production). Is it possible to force a reboot from I2C without physically replugging the device ??? (which we want to avoid of course during production)
Another option would be to, after programming the firmware into eeprom, load the same firmware again into RAM and run this firmware for the next steps, but this is not the preferred solution (cleaner would be to really reboot from the eeprom which verifies the eeprom to be correct)
Any input appreciated,
Jon
Hi,
Firstly say hello to all:) I want to build one kind of USB key,it has two USB connectors, when we connect it to two PCs via USB port, this two PCs can access its data simultaneously. We want to use Cypress's West Bridge Astoria as key solution. West Bridge Astoria already have one USB port, we will use another component, FX3S for example, convert P port to USB so that it have another USB port. Because this USB key want to be used under DOS or EFI or WinPE environment, my question is: for the USB port on Astoria chip, could it be recognized under DOS or EFI as normal USB key does ? or it only can be used under Windows by corresponding SW driver support ? I like to confirm before we move forward, thanks you very much in advance!
Hi:
I want to ask : can I create two threads for the two usb device, and the two usb devices work at the same time。
I find (Home › Cypress Developer Community › Forums )
http://www.cypress.com/forum/usb-high-speed-peripherals/multiple-usb-dev...
A developer said : you cannot communicate with two devices at the same time using CyAPI.lib.
Now, Actually, I use two usb devices, One thread one device, another thread to another device.
when I open second usb device by USBDevice->Open(1)，the first device will be closed?
in the C++ helpful doc (CyAPI.chm), When Open( ) is called, it first checks to see if the CCyUSBDevice object is already opened to one of the attached devices. If so, it calls Close( ), then proceeds.
It means that, at first I can't USBDevice->Open(0) in the first thread, and then USBDevice->Open(1) in the second thread.
Hello,
Can you tell me if there is a driver WIN10 for device cy7c68001
Best regards
Alain
FPGA 与68013A(100PIN) 采用Slave FIFO接口，BULK传输 ， 使用 EP2 OUT EP6 IN ,自动提交包方式，full speed模式，16bitBUS.异步方式（参见代码）
问题一）为什么数据 在IN 方向上只有8bit的数据是正确的？ 在OUT方向上也只有8bit的数据正确，而且只能正确传输奇数序列的数据。是不是贵公司的产品设计就是这样的？（数据参照如附件）？
问题二）数据手册中给出的IFCLOCK 的频率是5-48Mhz，而设计指导AN63787 中给出的RD和wr的时序参考，最大频率大约是8MHZ，（实测中超过5MHZ，基本上就全部乱码了。），请问一下，slaveFIFO 接口方式，正确的最大频率应设置多少合适？
哪位能解答一下，谢谢！
/********************************************************************************/
IFCONFIG = 0x8b;//0x0b;//0xCB; //30MHZ
// we are just using the default values, yes this is not necessary...
EP1OUTCFG = 0xA0;
EP1INCFG = 0xA0;
SYNCDELAY; // see TRM section 15.14
EP2CFG = 0xA2;
SYNCDELAY; //
EP4CFG = 0xA0;
SYNCDELAY; //
EP6CFG = 0xE2;
SYNCDELAY; //
EP8CFG = 0XE0;
EP2FIFOCFG = 0x11;SYNCDELAY;
EP4FIFOCFG = 0x11;SYNCDELAY;
EP6FIFOCFG = 0x09;SYNCDELAY;
EP8FIFOCFG = 0x09;SYNCDELAY;
EP6BCL = 0x80;SYNCDELAY;
EP6BCL = 0x80;SYNCDELAY;
EP8BCL = 0x80;SYNCDELAY;
EP8BCL = 0x80;SYNCDELAY;
// out endpoints do not come up armed
// since the defaults are double buffered we must write dummy byte counts twice
SYNCDELAY; //
EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
SYNCDELAY; //
EP4BCL = 0x80;
SYNCDELAY; //
EP2BCL = 0x80; // arm EP4OUT by writing byte count w/skip.
SYNCDELAY; //
EP4BCL = 0x80;
PORTACFG =0x40;
// fill up both IN endpoints
// for (i=0;i<512;i++)
// EP6FIFOBUF[i] = i+2;
// SYNCDELAY; //
// EP6BCH = 0x02;
// SYNCDELAY; //
// EP6BCL = 0x00;
//
// for (i=0;i<512;i++)
// EP6FIFOBUF[i] = i+2;
// SYNCDELAY; //
// EP6BCH = 0x02;
// SYNCDELAY; //
// EP6BCL = 0x00;
// myBufferCount = 0;
// enable dual autopointer(s)
// AUTOPTRSETUP |= 0x01;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
IFCONFIG =0x8b;// 0x0b;
// if EP6 IN is available, re-arm it
if(!(EP2468STAT & bmEP6FULL))
{
SYNCDELAY;
EP6BCH = 0x02;
SYNCDELAY; //
EP6BCL = 0x00;
//memset(EP6FIFOBUF,0x00,1024);
}
// if there is some data in EP2 OUT, re-arm it
if(!(EP2468STAT & bmEP2EMPTY))
{
SYNCDELAY; //
EP2BCL = 0x80;
}
/************************************************************************************/
Hi,
Im using FX2LP with endpoint 2 and 4 configured as BULK OUT double buffered 512 byte in MANUAL mode, and EP 6 and 8 configured as IN endpoint ISOCRONOUS double buffered 521 byte. Data are sent from PC, FX2LP CPU access data and commit manually all data packets to an external device accessing data through slave FIFO.
I have a strange beahviour whn PC host is sending data to OUT endpoint:
When FX2LP receive an OUT transfer from PC, ep2inout or ep4inout interrupt is triggering - depending from ep target -, and CPU make some access to fifo data, then commit data to slave fifo. Sometimes, when I have an element in fifo and when two packets are coming closely in time (about 100 uSec) CPU read data from endpoint fifo buffer but some data are from first packet, and other data are from second packet. It seems that, while CPU extracts data from endpoint fifo, data are changing. It seems that data packets is copied in fifo buffer from USB even if I have not committed packet, and endpoint is in manual mode. Before access data I verify that fifo is not empty with EP2468STAT register and I commit data only at the end of cpu accesses.
If I examine usb traffic with LeCroy T3 advisor protocol analyzer, I see that second packets has an initial NYET, then it seems ok, and only after time it receives an ACK.
I have an external microcontroller that extracts data from slave fifo, and it receive data packets correctly, then data are correct in fifo buffer, there is only problem with CPU access.
Has anyone any idea?
Thanks,
Begos
hi,
I have a FX2LP configured in slave fifo (with an external device that is reading data). I have endpoint 2 and 4 configured as bulk endpoint in manual mode, with buffered 2x of 512 byte length.
I would know if when 8051's FX2LP is accessing fifo data - before commit packet - is a safe practice, even if external device is reading data from slave fifo. 8051 checks fifo empty flag before accessdata, and external device checks hardware empty flag before read data from slave fifo.
What is the point of view of Cypress? Is there something to do for safety?
Best Regards
begos
Hi all
I design a board for spartan 6 and for connect to laptop need to full speed mode (2 layer pcb) but I can not use a full speed controller. can I use cy7c68013 in full mode(12 mb).I confuse to interface spartan 6 to cy7c68013 in full mode . I design interface in this picture.
I have a TI micro controller collecting sensor data which I need to send to a C# application. I did get the EZ-USB FX2LP DEV KIT and on the first glance it looks like a possible solution with working examples both on the PC and the FX2LP side. I need to transfer 3,200,000 bytes every second and the FX2LP seem to have the bandwidth. I also have to send some stuff to the micro from the PC but that is limited to about 256 bytes/second.
I would prefer a 16 bit connection between my micro and the FX2LP where the micro is the master and it writes to the FX2LP on its own heart beat. The micro is collecting data from 2 sensors and controlling a motor and already has way to many interrupts so i would like to communicate with the FX2LP as a master. Scanning trough the examples included with the dev kit I see a FIFO app that is made for 16 bits but the FX2LP is the master. Is there a way to make the FX2LP the slave?
Hi all,
I am trying to understande how GPIF works and following the document "Getting Started with EZ-USB® FX2LP™ GPIF".
When I open the attached source code of this document, I find there is no main.c file in the folder "FX2LP Source code and GPIF project files\Firmware\GPIF Clock Divider". I tried to type it manually, but when I tried to compile it, in the keil the build output always shows:
Rebuild target 'Target 1'
compiling main.c...
compiling GPIF_div_2_4.c...
linking...
BL51 BANKED LINKER/LOCATER V4.03 - SN: MSC1210
COPYRIGHT KEIL ELEKTRONIK GmbH 1987 - 2000
"main.obj",
"GPIF_div_2_4.obj",
".\EZUSB.LIB"(EZREGS)
TO "GPIF_Clock_Divider_Proj"
RAMSIZE(256)
CODE( 0x0080 )
XDATA( 0x1000 )
*** FATAL ERROR L220: INVALID INPUT MODULE
MODULE: .\EZUSB.LIB (EZREGS)
Target not created.
Build Time Elapsed: 00:00:00
Can anyone help me out?
Thanks!
hi all.
I'm new with Cypress Chips.
I have Some question's.
Can i Configure any Xilinx's FPGA with FX2LP Chips For example any spartan family ??
based on AN63620 i have to IFCLK pin to CCLK but is there different way that i configure FPGA wihout this pin?
i want to use ths pin for slave fifo interface....
thanks alot...
Hi,
I have a general question about the data structure used in the BeginDataXfer(), WaitForXfer() and FinishDataXfer() methods. I am following the C# examples provided. My doubt is related how to extract the data received after the next piece of code:
EndPoint.FinishDataXfer(ref cBufs[k], ref xBufs[k], ref len, ref oLaps[k])
If the transactions was sucesfull I have a filled xBufs buffer, but my question is related how to extract the "clean" data, it means only the data received. In this example I have 16 packets per Xfer and 8 Xfers to queue. This way xBufs is an array of 8 by 8192 bytes of size.
Hi,
Firstly say hello to all:) I want to build one kind of USB key,it has two USB connectors, when we connect it to two PCs via USB port, this two PCs can access its data simultaneously. We want to use Cypress's West Bridge Astoria as key solution. West Bridge Astoria already have one USB port, we will use another component, FX3S for example, convert P port to USB so that it have another USB port. Because this USB key want to be used under DOS or EFI or WinPE environment, my question is: for the USB port on Astoria chip, could it be recognized under DOS or EFI as normal USB key does ? or it only can be used under Windows by corresponding SW driver support ? I like to confirm before we move forward, thanks you very much in advance!
Is there is any utlity which converts eeprom iic file to intel hex
Hi all.
I'm almost new with FX2LP devices
One part of my project is transmitting data in rate 60Mbyte/s .
I want to use CY7C68013A for this purpose.
In PC side i have to develop soft ware which communicate with my board.
is it possible to use no external memory at all and every time the soft ware started it program CY7 individually ??
thanks.
